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| TMS470R1B512 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 FEATURES * * High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDMITM) - 24-MHz System Clock (60-MHz Pipeline Mode) - Independent 16/32-Bit Instruction Set - Open Architecture With Third-Party Support - Built-In Debug Module - Utilizes Big-Endian Format Integrated Memory - 512K-Byte Program Flash * 2 Banks With 14 Contiguous Sectors * Internal State Machine for Programming and Erase - 32K-Byte Static RAM (SRAM) 27 Dedicated General-Purpose Input/Output (GIO) Pins, 1 Input-Only GIO Pin, and 59 Additional Peripheral I/Os Operating Features - Core Supply Voltage (VCC): 1.81 V - 2.05 V - I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V - Low-Power Modes: STANDBY and HALT - Extended Industrial Temperature Range 470+ System Module - 32-Bit Address Space Decoding - Bus Supervision for Memory and Peripherals - Analog Watchdog (AWD) Timer - Real-Time Interrupt (RTI) - System Integrity and Failure Detection - Interrupt Expansion Module (IEM) Direct Memory Access (DMA) Controller - 32 Control Packets and 16 Channels Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler - Multiply-by-4 or -8 Internal ZPLL Option - ZPLL Bypass Mode * * * * * * * * * * * * (1) * * External Clock Prescale (ECP) Module - Programmable Low-Frequency External Clock (CLK) Seven Communication Interfaces: - Three Serial Peripheral Interfaces (SPIs) * 255 Programmable Baud Rates - Two Serial Communications Interfaces (SCIs) * 224 Selectable Baud Rates * Asynchronous/Isosynchronous Modes * Two High-End CAN Controllers (HECCs) * 32-Mailbox Capacity Each * Fully Compliant With CAN Protocol, Version 2.0B High-End Timer (HET) - 32 Programmable I/O Channels: * 24 High-Resolution Pins * 8 Standard-Resolution Pins - High-Resolution Share Feature (XOR) - High-End Timer RAM * 128-Instruction Capacity 16-Channel 10-Bit Multi-Buffered ADC (MibADC) - 128-Word FIFO Buffer - Single- or Continuous-Conversion Modes - 1.55 s Minimum Sample and Conversion Time - Calibration Mode and Self-Test Features Eight External Interrupts Flexible Interrupt Handling On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM). All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright (c) 2005-2006, Texas Instruments Incorporated ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com TMS470R1B512 144-Pin PGE Package (Top View) ADIN[0] ADIN[1] ADIN[2] ADIN[3] ADIN[4] ADIN[15] ADIN[5] ADIN[6] ADIN[7] ADEVT SPI3ENA SPI3SCS SPI3SIMO SPI3SOMI SPI3CLK VCC VSS SCI1RX SCI1TX SCI1CLK CAN1HTX CAN1HRX VCC VSS GIOB[7] CLKOUT VCCIO VSSIO HET[9] HET[8] GIOB[6] GIOB[5] TCK TDO TDI PLLDIS ADIN[11] ADIN[14] ADIN[10] ADIN[13] ADIN[9] ADIN[12] ADIN[8] ADREFHI ADREFLO VCCAD VSSAD TMS TMS2 GIOC[0] HET[23] HET[25] HET[26] HET[27] VSS VCC HET[0] HET[1] VSS VCC FLTP2 FLTP1 VCCP VSS HET[2] HET[3] HET[4] HET[5] HET[6] HET[7] GIOC[1] GIOC[2] 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 AWD HET[18] HET[19] HET[20] HET[21] HET[22] SPI2SCS SPI2ENA SPI2SOMI SPI2SIMO SPI2CLK GIOB[4] GIOB[3] GIOB[2] GIOB[1] CAN2HRX CAN2HTX VCC VSS VCCIO VSSIO HET[24] HET[31] HET[30] HET[29] HET[28] GIOB[0] SCI2CLK SCI2TX SCI2RX GIOA[3]/INT[3] GIOA[2]/INT[2] GIOA[1]/INT[1]/ECLK GIOA[0]/INT[0](A) TEST TRST A. GIOA[0]/INT0 (pin 39) is an input-only GIO pin. 2 SPI1ENA SPI1SCS SPI1SIMO SPI1SOMI SPI1CLK GIOC[3] GIOC[4] GIOC[5] GIOC[6] GIOC[7] VSS OSCOUT OSCIN VCC RST VSSIO VCCIO GIOD[3] GIOD[2] GIOD[1] GIOD[0] HET[17] HET[16] HET[15] HET[14] HET[13] HET[12] HET[11] HET[10] VSS VCC PORRST GIOA[7]/INT[7] GIOA[6]/INT[6] GIOA[5]/INT[5] GIOA[4]/INT[4] ADVANCE INFORMATION Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 DESCRIPTION The TMS470R1B512 (1) device is a member of the Texas Instruments (TI) TMS470R1x family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The B512 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The B512 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B512 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The B512 device contains the following: * ARM7TDMI 16/32-Bit RISC CPU * TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM) and a 16-channel direct-memory access (DMA) controller] * 512K-byte flash * 32K-byte SRAM * Zero-pin phase-locked loop (ZPLL) clock module * Analog watchdog (AWD) timer * Real-time interrupt ( RTI) module * Three serial peripheral interface (SPI) modules * Two serial communications interface (SCI) modules * Two high-end CAN controller (HECC) modules * 10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels * High-end timer (HET) controlling 32 I/Os * External clock prescale (ECP) module * Up to 86 I/O pins and 1 input-only pin The functions performed by the 470+ system module (SYS) include: * Address decoding * Memory protection * Memory and peripherals bus supervision * Reset and abort exception management * Expanded interrupt capability with prioritization for all internal interrupt sources * Device clock control * Direct-memory access (DMA) and control * Parallel signature analysis (PSA). This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). For a more detailed functional description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). For a more detailed functional description of the DMA module, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194). The B512 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. (1) The TMS470R1B512 device name will be referred to as either the full device name or as B512 throughout the remainder of this document. Submit Documentation Feedback 3 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information on the F05 devices flash, see the F05 Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). The B512 device has seven communication interfaces: three SPIs, two SCIs, and two HECCs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). The B512 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET highresolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). The B512 device has a 10-bit-resolution, 16-channel sample-and-hold MibADC. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B512 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212). NOTE: ADVANCE INFORMATION ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference. The B512 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202). 4 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Device Characteristics The B512 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all the characteristics of the B512 device except the SYSTEM and CPU, which are generic. Table 1. Device Characteristics CHARACTERISTICS DEVICE DESCRIPTION TMS470R1B512 MEMORY For the number of memory selects on this device, see Table 3, Memory Selection Assignment. INTERNAL MEMORY Pipeline/Non-Pipeline 512K-Byte flash 32K-Byte SRAM Flash is pipeline-capable. The B512 RAM is implemented in one 32K array selected by two memory-select signals (see Table 3, Memory Selection Assignment). PERIPHERALS For the device-specific interrupt priority configurations, see Table 7, Interrupt Priority (IEM and CIM). And for the 1K peripheral address ranges and their peripheral selects, see Table 5, A512 Peripherals, System Module, and Flash Base Addresses. CLOCK GENERAL-PURPOSE I/Os ECP SCI CAN (HECC and/or SCC) SPI (5-pin, 4-pin or 3-pin) ZPLL 27 I/O 1 Input only YES 2 (3-pin) 2 HECCs 3 (5-pin) SCI1 and SCI2 Two high-end CAN controller modules (HECC1 and HECC2) SPI1, SPI2, and SPI3 The B512 device has both the logic and registers for a full 32-I/O HET implemented and all 32 pins are available externally. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). The B512 device has both the logic and registers for a full 16-channel MibADC implemented and all 16 pins are available externally. Zero-pin PLL has no external loop filter pins. Ports A, B, and C each have eight (8) external pins. Port D has four (4) external pins. COMMENTS HET with XOR Share 32 I/O HET RAM MibADC CORE VOLTAGE I/O VOLTAGE PINS PACKAGE 128-Instruction Capacity 10-bit, 16-channel 128-word FIFO 1.81 - 2.05 V 3.0 - 3.6 V 144 PGE Submit Documentation Feedback 5 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Functional Block Diagram OSCIN OSCOUT PLLDIS ADIN[15:0] ADEVT ADREFHI ADREFLO VCCAD VSSAD HET [31:24] HET[23:0] CAN1HTX CAN1HRX CAN2HTX CAN2HRX SCI1CLK SCI1TX SCI1RX SCI2CLK SCI2TX SCI2RX Crystal External Pins VCCP FLTP1 FLTP2 ZPLL FLASH (512K Bytes) 14 Sectors RAM (32K Bytes) MibADC with 128-Word FIFO External Pins CPU Address/Data Bus TRST TCK TDI TDO TMS TMS2 RST AWD TEST PORRST CLKOUT TMS470R1x CPU Expansion Address/Data Bus HET with XOR Share (128-Word) HECC1 HECC2 TMS470R1x System Module GIOA[1]/INT[1]/ ECLK GIOA[2:7]/ INT[2:7] GIOB[0:7] GIOC[0:7] GIOD[0:3] SPI2SCS SPI2ENA SPI2SIMO SPI2SOMI SPI2CLK A. GIOA[0]/INT0 is an input-only pin. 6 GIOA[0]/INT[0](A) Submit Documentation Feedback SPI3SCS SPI3ENA SPI3SIMO SPI3SOMI SPI3CLK SPI1SCS SPI1ENA SPI1SIMO SPI1SOMI SPI1CLK ADVANCE INFORMATION DMA Controller 16 Channels Interrupt Expansion Module (IEM) SCI1 SCI2 ECP GIO SPI3 SPI2 SPI1 www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Table 2. Terminal Functions TERMINAL NAME NO. TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) HIGH-END TIMER (HET) HET[0] HET[1] HET[2] HET[3] HET[4] HET[5] HET[6] HET[7] HET[8] HET[9] HET[10] HET[11] HET[12] HET[13] HET[14] HET[15] HET[16] HET[17] HET[18] HET[19] HET[20] HET[21] HET[22] HET[23] HET[24] HET[25] HET[26] HET[27] HET[28] HET[29] HET[30] HET[31] CAN1HTX CAN1HRX CAN2HTX CAN2HRX (1) (2) (3) 129 130 137 138 139 140 141 142 79 80 29 28 27 26 25 24 23 22 71 70 69 68 67 123 51 124 125 126 47 48 49 50 HIGH-END CAN CONTROLLER 1 (HECC1) 88 87 56 57 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O IPU (20 A) IPU (20 A) HECC1 transmit pin or GIO pin HECC1 receive pin or GIO pin HIGH-END CAN CONTROLLER 2 (HECC2) HECC2 transmit pin or GIO pin HECC2 receive pin or GIO pin 3.3-V I/O IPD (20 A) DESCRIPTION I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) Submit Documentation Feedback 7 ADVANCE INFORMATION The B512 device has both the logic and registers for a full 32-I/O HET implemented and all 32 pins are available externally. Timer input capture or output compare. The HET[31:0] applicable pins can be programmed as general-purpose input/output (GIO) pins. HET[23:0] are high-resolution pins and HET[31:24] are standard-resolution pins. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME NO. TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) GENERAL-PURPOSE I/O (GIO) GIOA[0]/INT0 GIOA[1]/INT1/ ECLK GIOA[2]/INT2 GIOA[3]/INT3 GIOA[4]/INT4 GIOA[5]/INT5 GIOA[6]/INT6 GIOA[7]/INT7 GIOB[0] GIOB[1] GIOB[2] 39 40 41 42 36 35 34 33 46 58 59 60 61 77 78 84 122 143 144 6 7 8 9 10 21 20 19 18 MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) ADEVT ADIN[0] ADIN[1] ADIN[2] ADIN[3] ADIN[4] ADIN[5] ADIN[6] ADIN[7] ADIN[8] ADIN[9] ADIN[10] ADIN[11] ADIN[12] 99 108 107 106 105 104 102 101 100 115 113 111 109 114 3.3-V I MibADC analog input pins 3.3-V I/O IPD (20 A) MibADC event input. ADEVT can be programmed as a GIO pin. 3.3-V I/O IPD (20 A) General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin. GIOA[7:0]/INT[7:0] are interrupt-capable pins. The GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out function of the external clock prescale (ECP) module. 3.3-V I DESCRIPTION ADVANCE INFORMATION 8 GIOB[3] GIOB[4] GIOB[5] GIOB[6] GIOB[7] GIOC[0] GIOC[1] GIOC[2] GIOC[3] GIOC[4] GIOC[5] GIOC[6] GIOC[7] GIOD[0] GIOD[1] GIOD[2] GIOD[3] Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Table 2. Terminal Functions (continued) TERMINAL NAME NO. TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) DESCRIPTION MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) (CONTINUED) ADIN[13] ADIN[14] ADIN[15] ADREFHI ADREFLO VCCAD VSSAD SPI1CLK SPI1ENA SPI1SCS SPI1SIMO SPI1SOMI 112 110 103 116 117 118 119 5 1 2 3.3-V I/O 3 4 IPD (20 A) 3.3-V REF I GND REF I 3.3-V PWR GND MibADC module high-voltage reference input MibADC module low-voltage reference input MibADC analog supply voltage MibADC analog ground reference SERIAL PERIPHERAL INTERFACE 1 (SPI1) SPI1 clock. SPI1CLK can be programmed as a GIO pin. SPI1 chip enable. SPI1ENA can be programmed as a GIO pin. SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin. SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin. SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE 2 (SPI2) SPI2CLK SPI2ENA SPI2SCS SPI2SIMO SPI2SOMI 62 65 66 3.3-V I/O 63 64 IPD (20 A) SPI2 clock. SPI2CLK can be programmed as a GIO pin. SPI2 chip enable. SPI2ENA can be programmed as a GIO pin. SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin. SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a GIO pin. SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE 3 (SPI3) SPI3CLK SPI3ENA SPI3SCS SPI3SIMO SPI3SOMI 94 98 97 3.3-V I/O 96 95 IPD (20 A) SPI3 clock. SPI3CLK can be programmed as a GIO pin. SPI3 chip enable. SPI3ENA can be programmed as a GIO pin. SPI3 slave chip select. SPI3SCS can be programmed as a GIO pin. SPI3 data stream. Slave in/master out. SPI3SIMO can be programmed as a GIO pin. SPI3 data stream. Slave out/master in. SPI3SOMI can be programmed as a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN OSCOUT PLLDIS 13 12 73 1.8-V I 1.8-V O 3.3-V I IPD (20 A) Crystal connection pin or external clock input External crystal connection pin Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SCI2 clock. SCI2CLK can be programmed as a GIO pin. SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2 data transmit. SCI2TX can be programmed as a GIO pin. 3.3-V I MibADC analog input pins SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK SCI1RX SCI1TX SCI2CLK SCI2RX SCI2TX 89 91 90 45 43 44 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O IPD (20 A) IPU (20 A) IPU (20 A) IPD (20 A) IPU (20 A) IPU (20 A) SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) Submit Documentation Feedback 9 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NAME NO. TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) SYSTEM MODULE (SYS) CLKOUT PORRST 83 32 3.3-V I/O 3.3-V I IPD (20 A) IPD (20 A) Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK, ICLK, or MCLK. Input master chip power-up reset. External VCC monitor circuitry must assert a power-on reset. Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. On this pin, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not written in time by the system, providing an external RC network circuit is connected. If the user is not using AWD, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. For more details on the external RC network circuit, see the TMS470R1x System Module Reference Guide (literature number SPNU189). TEST/DEBUG (T/D) TCK TDI TDO TEST TMS TMS2 TRST 76 74 75 38 120 121 37 3.3-V I 3.3-V I 3.3-V O 3.3-V I 3.3-V I 3.3-V I 3.3-V I IPD (20 A) IPU (20 A) IPD (20 A) IPD (20 A) IPU (20 A) IPU (20 A) IPD (20 A) Test clock. TCK controls the test hardware (JTAG). Test data in. TDI inputs serial data to the test instruction register, test data register, and programmable test address (JTAG). Test data out. TDO outputs serial data from the test instruction register, test data register, identification register, and programmable test address (JTAG). Test enable. Reserved for internal use only. TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. Serial input for controlling the state of the CPU test access port (TAP) controller (JTAG) Serial input for controlling the second TAP. TI recommends that this pin be connected to VCCIO or pulled up to VCCIO by an external resistor. Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic. TI recommends that this pin be pulled down to ground by an external resistor. FLASH FLTP1 FLTP2 VCCP 134 133 135 NC NC 3.3-V PWR Flash test pad 1. For proper operation, this pin must not be connected [no connect (NC)]. Flash test pad 2. For proper operation, this pin must not be connected [no connect (NC)]. Flash external pump voltage (3.3 V). This pin is required for both flash read and flash program and erase operations. SUPPLY VOLTAGE CORE (1.8 V) 14 31 55 VCC 86 93 128 132 1.8-V PWR Core logic supply voltage DESCRIPTION RST 15 3.3-V I/O IPU (20 A) WATCHDOG/REAL-TIME INTERRUPT (WD/RTI) AWD 72 3.3-V I/O IPD (20 A) ADVANCE INFORMATION 10 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Table 2. Terminal Functions (continued) TERMINAL NAME NO. TYPE (1) (2) INTERNAL PULLUP/ PULLDOWN (3) SUPPLY VOLTAGE DIGITAL I/O (3.3 V) 17 VCCIO 53 82 SUPPLY GROUND CORE 11 30 54 VSS 85 92 127 131 SUPPLY GROUND DIGITAL I/O 16 VSSIO 52 81 GND Digital I/O supply ground reference 136 GND Core supply ground reference 3.3-V PWR Digital I/O supply voltage DESCRIPTION Submit Documentation Feedback 11 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com B512 Device-Specific Information Memory Figure 1 shows the memory map of the B512 device. Memory (4G Bytes) 0xFFFF_FFFF System Module Control Registers (512K Bytes) SYSTEM with PSA, CIM, RTI, DEC, DMA, MMC IEM Reserved Peripheral Control Registers (512K Bytes) 0xFFF0_0000 0xFFEF_FFFF 0xFFE8_C000 0xFFE8_BFFF 0xFFE8_8000 0xFFE8_7FFF 0xFFE8_4024 0xFFE8_4023 0xFFE8_4000 0xFFE8_3FFF HET Reserved SPI1 Flash Control Registers SCI2 Reserved SCI1 MPU Control Registers MibADC 0xFFF7_F000 Reserved 0xFFE0_0000 HECC1/HECC2 0xFFF7_E800 HECC1/2 RAM 0xFFF7_E400 Reserved RAM (32K Bytes) 0xFFF7_D800 SPI2/SPI3 0xFFF7_D400 Program and Data Area FLASH (512K Bytes) 14 Sectors Reserved 0xFFF7_C000 Reserved 0xFFF0_0000 HET RAM (1.5K Bytes) FIQ IRQ Reserved 0x0000_0014 Data Abort 0x0000_0010 0x0000_0020 0x0000_001F Exception, Interrupt, and Reset Vectors 0x0000_0000 Prefetch Abort 0x0000_000C Software Interrupt 0x0000_0008 Undefined Instruction Reset 0x0000_0004 0x0000_0000 0x0000_001F 0x0000_001C 0x0000_0018 GIO/ECP 0xFFF7_EC00 0xFFF7_F400 0xFFF7_F500 0xFFF7_F800 0xFFF7_FC00 0xFFFF_FFFF 0xFFFF_FD00 0xFFFF_FC00 0xFFF8_0000 0xFFF8_0000 0xFFF7_FFFF ADVANCE INFORMATION 12 A. B. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000. The CPU registers are not a part of the memory map. Figure 1. Memory Map Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Memory Selects Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx and MFBALRx) that, together, define the array's starting (base) address, block size, and protection. The base address of each memory select is configurable to any memory address boundary that is a multiple of the decoded block size. For more information on how to control and configure these memory select registers, see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number SPNU189). For the memory selection assignments and the memory selected, see Table 3. Table 3. Memory Selection Assignment MEMORY SELECT 0 (fine) 1 (fine) 2 (fine) 3 (fine) 4 (fine) (1) MEMORY SELECTED (ALL INTERNAL) FLASH FLASH RAM RAM HET RAM MEMORY SIZE 512K 32K (1) 1.5K MPU NO NO YES YES MEMORY BASE ADDRESS REGISTER MFBAHR0 and MFBALR0 MFBAHR1 and MFBALR1 MFBAHR2 and MFBALR2 MFBAHR3 and MFBALR3 MFBAHR4 and MFBALR4 SMCR1 STATIC MEM CTL REGISTER The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the memory-base address register. RAM The B512 device contains 32K bytes of internal static RAM configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. This B512 RAM is implemented in one 32K array selected by two memory-select signals. This B512 configuration imposes an additional constraint on the memory map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of the physical RAM (i.e., 32K for the B512 device). The B512 RAM is addressed through memory selects 2 and 3. The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an operating system while allowing access to the current task. For more detailed information on the MPU portion of the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference Guide (literature number SPNU189). F05 Flash The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The F05 flash has an external state machine for program and erase functions. See the flash read and flash program and erase sections below. For more detailed functional information on the F05 flash module, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). Flash Protection Keys The B512 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/compaction operations from occurring until after the four protection keys have been matched by the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B512 are located in the last 4 words of the first 16K sector. For more detailed information on the flash protection keys and the FMPKEY control register, see the "Optional Quadruple Protection Keys" and "Programming the Protection Keys" portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). Submit Documentation Feedback 13 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Flash Read The B512 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1. NOTE: The flash external pump voltage (VCCP) is required for all operations (program, erase, and read). Flash Pipeline Mode When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. In normal mode, the flash operates with a system clock frequency in normal mode of up to 24 MHz. Flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash can be read with no wait states when memory addresses are contiguous (after the initial 1-or 2-wait-state reads). NOTE: After a system reset, pipeline mode is disabled (FMREGOPT[0] = 0). In other words, the B512 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash configuration mode bit (GBLCTRL[4]) will override pipeline mode. Flash Program and Erase ADVANCE INFORMATION The B512 device flash contains two 256K-byte memory arrays (or banks) for a total of 512K bytes of flash and consists of fourteen sectors. These fourteen sectors are sized as follows: Table 4. B512 Flash Memory Banks and Sectors SECTOR NO. 0 1 2 3 4 5 6 7 8 9 0 1 2 3 SEGMENT 16K Bytes 16K Bytes 32K Bytes 32K Bytes 32K Bytes 32K Bytes 32K Bytes 32K Bytes 16K Bytes 16K Bytes 64K Bytes 64K Bytes 64K Bytes 64K Bytes LOW ADDRESS 0x00000000 0x00004000 0x00008000 0x00010000 0x00018000 0x00020000 0x00028000 0x00030000 0x00038000 0x0003C000 0x00040000 0x00050000 0x00060000 0x00070000 HIGH ADDRESS 0x00003FFF 0x00007FFF 0x0000FFFF 0x00017FFF 0x0001FFFF 0x00027FFF 0x0002FFFF 0x00037FFF 0x0003BFFF 0x0003FFFF 0x0004FFFF 0x0005FFFF 0x0006FFFF 0x0007FFFF BANK1 (256K Bytes) BANK0 (256K Bytes) MEMORY ARRAYS (OR BANKS) The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit word. NOTE: The flash external pump voltage (VCCP) is required for all operations (program, erase, and read). For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). 14 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 HET RAM The B512 device contains HET RAM. The HET RAM has a 128-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET RAM is addressed through memory select 4. Peripheral Selects and Base Addresses The B512 device uses 8 of the 16 peripheral selects to decode the base addresses of the peripherals. These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the SYS module. Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 5. Table 5. B512 Peripherals, System Module, and Flash Base Addresses CONNECTING MODULE SYSTEM RESERVED PSA CIM RTI DMA DEC MMC IEM RESERVED RESERVED DMA CMD BUFFER RESERVED RESERVED HET RESERVED SPI1 RESERVED SCI2 SCI1 RESERVED MibADC ECP RESERVED GIO HECC2 HECC1 HECC2 RAM HECC1 RAM RESERVED RESERVED RESERVED RESERVED SPI3 SPI2 RESERVED ADDRESS RANGE BASE ADDRESS 0 x FFFF_FFD0 0 x FFFF_FF60 0 x FFFF_FF40 0 x FFFF_FF20 0 x FFFF_FF00 0 x FFFF_FE80 0 x FFFF_FE00 0 x FFFF_FD00 0 x FFFF_FC00 0 x FFFF_FB00 0 x FFFF_FA00 0 x FFFF_F800 0 x FFF8_0000 0 x FFF7_FD00 0 x FFF7_FC00 0 x FFF7_F900 0 x FFF7_F800 0 x FFF7_F600 0 x FFF7_F500 0 x FFF7_F400 0 x FFF7_F100 0 x FFF7_F000 0 x FFF7_EF00 0 x FFF7_ED00 0 x FFF7_EC00 0 x FFF7_EA00 0 x FFF7_E800 0 x FFF7_E600 0 x FFF7_E400 0 x FFF7_E000 0 x FFF7_DC00 0 x FFF7_D800 0 x FFF7_D600 0 x FFF7_D500 0 x FFF7_D400 0 x FFF7_C000 ENDING ADDRESS 0 x FFFF_FFFF 0 x FFFF_FFCF 0 x FFFF_FF5F 0 x FFFF_FF3F 0 x FFFF_FF1F 0 x FFFF_FEFF 0 x FFFF_FE7F 0 x FFFF_FD7F 0 x FFFF_FCFF 0 X FFFF_FBFF 0 X FFFF_FAFF 0 x FFFF_F9FF 0 x FFFF_F7FF 0 x FFF7_FFFF 0 x FFF7_FCFF 0 x FFF7_FBFF 0 x FFF7_F8FF 0 x FFF7_F7FF 0 X FFF7_F5FF 0 x FFF7_F4FF 0 x FFF7_F3FF 0 x FFF7_F0FF 0 x FFF7_EFFF 0 x FFF7_EEFF 0 x FFF7_ECFF 0 x FFF7_EBFF 0 x FFF7_E9FF 0 x FFF7_E7FF 0 x FFF7_E5FF 0 x FFF7_E3FF 0 x FFF7_DFFF 0 x FFF7_DBFF 0 x FFF7_D7FF 0 x FFF7_D5FF 0 x FFF7_D4FF 0 x FFF7_D3FF PS[11] - PS[15] 15 PS[10] PS[5] PS[6] PS[7] PS[8] PS[9] PS[4] PS[3] PS[2] PERIPHERAL SELECTS N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PS[0] PS[1] Submit Documentation Feedback ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Table 5. B512 Peripherals, System Module, and Flash Base Addresses (continued) CONNECTING MODULE RESERVED FLASH CONTROL REGISTERS MPU CONTROL REGISTERS ADDRESS RANGE BASE ADDRESS 0 x FFF0_0000 0 x FFE8_8000 0 x FFE8_4000 ENDING ADDRESS 0 x FFF7_BFFF 0 x FFE8_BFFF 0 x FFE8_4023 PERIPHERAL SELECTS N/A N/A N/A Direct-Memory Access (DMA) The direct-memory access (DMA) controller transfers data to and from any specified location in the B512 memory map (except for restricted memory locations like the system control registers area). The DMA manages up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA controller is connected to both the CPU and Peripheral busses, enabling these data transfers to occur in parallel with CPU activity and thus, maximizing overall system performance. Although the DMA controller has two possible configurations, for the B512 device, the DMA controller configuration is 32 control packets and 16 channels. For the B512 DMA request hardwired configuration, see Table 6. For a more detailed functional description of the DMA module, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194). ADVANCE INFORMATION (1) 16 Table 6. DMA Request Lines Connections MODULES RESERVED SPI1 SPI1 MibADC (1) MibADC (1)/SCI1 MibADC (1)/SCI1 RESERVED SPI2 SPI2 RESERVED RESERVED RESERVED RESERVED RESERVED SCI2/SPI3 SCI2/SPI3 SCI2 end-receive/SPI3 end-receive SCI2 end-transmit/SPI3 end-transmit SCI2DMA0/SPI3DMA0 SCI2DMA1/SPI3DMA1 SPI2 end-receive SPI2 end-transmit SPI2DMA0 SPI2DMA1 SPI1 end-receive SPI1 end-transmit MibADC event MibADC G1/SCI1 end-receive MibADC G2/SCI1 end-transmit SPI1DMA0 SPI1DMA1 MibADCDMA0 MibADCDMA1/SCI1DMA0 MibADCDMA2/SCI1DMA1 DMA REQUEST INTERRUPT SOURCES DMA CHANNEL DMAREQ[0] DMAREQ[1] DMAREQ[2] DMAREQ[3] DMAREQ[4] DMAREQ[5] DMAREQ[6] DMAREQ[7] DMAREQ[8] DMAREQ[9] DMAREQ[10] DMAREQ[11] DMAREQ[12] DMAREQ[13] DMAREQ[14] DMAREQ[15] The MibADC is capable of being serviced by the DMA when the device is in buffered mode. For more information on buffered mode, see the MibADC section of this data sheet and the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable, and the channels determine the priority level of the interrupt. DMA transfers occur in one of two modes: * Non-request mode (used when transferring from memory to memory) * Request mode (used when transferring from memory to peripheral) For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194). Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Interrupt Priority (IEM to CIM) Interrupt requests originating from the B512 peripheral modules (i.e., SPI1, SPI2, or SPI3; SCI1 or SCI2; HECC1 or HECC2; RTI; etc.) are assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable register mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion of the SYS module. Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel between sources. The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the CIM to be of either type: * Fast interrupt request (FIQ) * Normal interrupt request (IRQ) The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel order in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their associated modules, see Table 7. Table 7. Interrupt Priority (IEM and CIM) MODULES SPI1 RTI RTI RTI SPI2 GIO RESERVED HET RESERVED SCI1/SCI2 SCI1 RESERVED RESERVED HECC1 RESERVED SPI3 MibADC SCI2 DMA RESERVED SCI1 System RESERVED HET HECC1 RESERVED SCI2 MibADC DMA GIO MibADC RESERVED Submit Documentation Feedback SCI2 transmit interrupt MibADC end Group 1 conversion DMA interrupt 1 GIO interrupt B MibADC end Group 2 conversion HET interrupt 2 HECC1 interrupt B SCI1 transmit interrupt SW interrupt (SSI) SPI3 end-transfer/overrun MibADC end event conversion SCI2 receive interrupt DMA interrupt 0 HECC1 interrupt A SCI1 or SCI2 error interrupt SCI1 receive interrupt HET interrupt 1 INTERRUPT SOURCES SPI1 end-transfer/overrun COMP2 interrupt COMP1 interrupt TAP interrupt SPI2 end-transfer/overrun GIO interrupt A IEM CHANNEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADVANCE INFORMATION DEFAULT CIM INTERRUPT LEVEL/CHANNEL TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Table 7. Interrupt Priority (IEM and CIM) (continued) MODULES RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HECC2 HECC2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HECC2 interrupt A HECC2 interrupt B INTERRUPT SOURCES DEFAULT CIM INTERRUPT LEVEL/CHANNEL 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 IEM CHANNEL 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ADVANCE INFORMATION For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the TMS470R1x System Module Reference Guide (literature number SPNU189). 18 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 MibADC The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a 10-bit digital value. The B512 MibADC module can function in two modes: compatibility mode, where its programmer's model is compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts or by the DMA. MibADC Event Trigger Enhancements The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC. * Both group1 and the event group can be configured for event-triggered operation, providing up to two event-triggered groups. * The trigger source and polarity can be selected individually for both group 1 and the event group from the three options identified in Table 8. Table 8. MibADC Event Hookup Configuration EVENT NO. EVENT1 EVENT2 EVENT3 EVENT4 SOURCE SELECT BITS FOR G1 OR EVENT (G1SRC[1:0] OR EVSRC[1:0]) 00 01 10 11 SIGNAL PIN NAME ADEVT HET18 HET19 RESERVED For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are configured via the event group source select bits (EVSRC[1:0]) in the AD event source register (ADEVTSRC[1:0]). For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). Submit Documentation Feedback 19 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Documentation Support Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of documentation available include: data sheets with design specifications; complete user's guides for all devices and development support tools; and hardware and software applications. Useful reference documentation includes: * Bulletin - TMS470 Microcontroller Family Product Bulletin (literature number SPNB086) * User's Guides - TMS470R1x System Module Reference Guide (literature number SPNU189) - TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192) - TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194) - TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number) SPNU195 - TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196) - TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197) - TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199) - TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202) - TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206) - TMS470R1x ZeroPin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212) - TMS470R1x F05 Flash Reference Guide (literature number SPNU213) - TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214) - TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218) - TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245) - TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246) - TMS470 Peripherals Overview Reference Guide (literature number SPNU248) * Errata Sheet - TMS470R1B512 TMS470 Microcontrollers Silicon Errata (literature number SPNZ141) ADVANCE INFORMATION 20 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Device Numbering Conventions Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family. TMS 470 R1 B PREFIX TMS = Fully Qualified Device FAMILY 470 = TMS470 RISC - Embedded Microcontroller Family ARCHITECTURE R1 = ARM7TDM1 CPU DEVICE TYPE B With 512K-Bytes Flash Memory: 60-MHz Frequency 1.8-V Core, 3.3-V I/O Flash Program Memory ZPLL Clock 32-Byte Static RAM 1.5K-Byte HET RAM (128 Instructions) Analog Watchdog (AWD) Real-Time Interrupt (RTI) 10-Bit, 12-Input MibADC Three SPI Modules Three SCI Modules Two CAN [HECC] modules HET, 32 Channels ECP DMA 512 PGE T OPTIONS TEMPERATURE T = -40C to 105C Q = -40C to 125C PACKAGE TYPE PGE = 144-pin Low-Profile Quad Flatpack (LQFP) REVISION CHANGE Blank = Original FLASH MEMORY 512 = 512K-Bytes Flash Memory Figure 2. TMS470R1x Family Nomenclature Submit Documentation Feedback 21 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Device Identification Code Register The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash device, and an assigned device-specific part number (see Figure 3). The B512 device identification code register value is 0xn92Fh. Figure 3. TMS470 Device ID Bit Allocation Register [offset = FFFF_FFF0h] 31 Reserved 15 VERSION 12 11 TF 10 R/F 9 PART NUMBER R-K 3 2 1 R-1 1 1 R-1 0 1 R-1 16 R-K R-K R-K LEGEND: R = Read only, -K = Value constant after RST; -n = Value after RST Table 9. TMS470 Device ID Bit Allocation Register Field Descriptions Bit 31-16 15-12 Field Reserved VERSION TF 0 1 10 R/F 0 1 9-3 2-0 PART NUMBER 1 Value Description Reads are undefined and writes have no effect. Silicon version (revision) bits. These bits identify the silicon version of the device. Initial device version numbers start at 0000. The current revision for the B512 device is 0010. Technology family bit. This bit distinguishes the technology family core power supply: 3.3 V for F10/C10 devices 1.8 V for F05/C05 devices ROM/flash bit. This bit distinguishes between ROM and flash devices: Flash device ROM device Device-specific part number bits. These bits identify the assigned device-specific part number. The assigned device-specific part number for the B512 device is 0100101. Mandatory High. Bits 2, 1, and 0 are tied high by default. ADVANCE INFORMATION 22 11 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Device Electrical Specifications and Timing Parameters Absolute Maximum Ratings over operating free-air temperature range, T version (unless otherwise noted) (1) Supply voltage range: Supply voltage range: Input voltage range: Input clamp current: VCC (2) VCCIO, VCCAD, VCCP (flash pump) All input pins IIK (VI < 0 or VI > VCCIO) All pins except ADIN[0:11], PORRST, TRST , TEST, and TCK IIK (VI < 0 or VI > VCCAD) ADIN[0:15] (2) -0.3 V to 2.5 V -0.3 V to 4.1V -0.3 V to 4.1V 20 mA 10 mA -40C to 105C -40C to 125C -65C to 150C Operating free-air temperature range, TA: Operating junction temperature ranges, TJ Storage temperature range, Tstg (1) (2) T version Q version Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds. Device Recommended Operating Conditions (1) MIN VCC VCCIO VCCAD VCCP VSS VSSAD TA TJ (1) Digital logic supply voltage (Core) Digital logic supply voltage (I/O) MibADC supply voltage Flash pump supply voltage Digital logic supply ground MibADC supply ground Operating free-air temperature Operating junction temperature All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD. T version Q version -0.1 -40 -40 -40 1.81 3 3 3 3.3 3.3 3.3 0 0.1 105 125 150 C NOM MAX 2.05 3.6 3.6 3.6 UNIT V V V V V V C Submit Documentation Feedback 23 ADVANCE INFORMATION -40C to 150C TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Electrical Characteristics over recommended operating free-air temperature range, T version (unless otherwise noted) (1) PARAMETER Vhys VIL Input hysteresis Low-level input voltage All inputs (2) except OSCIN OSCIN only VIH Vth RDSON VOL VOH High-level input voltage Input threshold voltage Drain to source on resistance Low-level output voltage (4) High-level output voltage (4) Input clamp current (I/O pins) (5) IIL Pulldown IIH Pulldown II Input current (I/O pins) IIL Pullup IIH Pullup All other pins CLKOUT, AWD, TDO IOL Low-level output current RST, SPInCLK, SPInSOMI, SPInSIMO All other output pins (6) CLKOUT, TDO RST, SPInCLK, SPInSOMI, SPInSIMO All other output pins except RST (6) SYSCLK = 60 MHz, ICLK = 20 MHz, VCC = 2.05 V SYSCLK = 24 MHz, ICLK = 12 MHz, VCC = 2.05 V OSCIN = 6 MHz, VCC = 2.05 V All frequencies, VCC = 2.05 V -8 -4 VOH = VOH MIN -2 125 85 4 2.0 mA mA mA mA mA VOL = VOL MAX All inputs except OSCIN OSCIN only AWD only AWD only (3) VOL = 0.35 V at IOL = 8 mA IOL = IOL MAX IOL = 50 A IOH = IOH MIN IOH = 50 A VI < VSSIO - 0.3 or VI > VCCIO + 0.3 VI = VSS VI = VCCIO VI = VSS VI = VCCIO No pullup or pulldown 0.8 VCCIO VCCIO - 0.2 -2 -1 5 -40 -1 -1 2 1 40 -5 1 1 8 4 2 mA A TEST CONDITIONS MIN 0.15 -0.3 -0.3 2 0.65 VCC 1.35 0.8 0.35 VCC VCCIO + 0.3 VCC + 0.3 1.8 45 0.2 VCCIO 0.2 V V V mA V TYP MAX UNIT V V ADVANCE INFORMATION IIC IOH High-level output current VCC Digital supply current (operating mode) ICC VCC Digital supply current (standby mode) (7) VCC Digital supply current (halt mode) (7) (1) (2) (3) (4) (5) (6) (7) 24 Source currents (out of the device) are negative while sink currents (into the device) are positive. This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section. These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide (literature number SPNU189). VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied. Parameter does not apply to input-only or output-only pins. The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value will always be low. For flash pumps/banks in sleep mode. Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Electrical Characteristics (continued) over recommended operating free-air temperature range, T version (unless otherwise noted) PARAMETER VCCIO Digital supply current (operating mode) ICCIO VCCIO Digital supply current (standby mode) VCCIO Digital supply current (halt mode) VCCAD supply current (operating mode) ICCAD VCCAD supply current (standby mode) VCCAD supply current (halt mode) TEST CONDITIONS No DC load, VCCIO = 3.6 V (8) No DC load, VCCIO = 3.6 V (8) No DC load, VCCIO = 3.6 V (8) All frequencies, VCCAD = 3.6 V All frequencies, VCCAD = 3.6 V All frequencies, VCCAD = 3.6 V VCCP = 3.6 V read operation VCCP = 3.6 V program and erase ICCP VCCP pump supply current VCCP = 3.6 V standby mode operation (7) VCCP = 3.6 V halt mode operation (7) CI CO (8) Input capacitance Output capacitance 2 3 MIN TYP MAX 10 300 300 15 20 20 55 70 20 20 UNIT mA A A mA A A mA mA A A pF I/O pins configured as inputs or outputs with no load. All pulldown inputs 0.2 V. All pullup inputs VCCIO - 0.2 V. Parameter Measurement Information IOL Tester Pin Electronics V LOAD 50 CL Output Under Test I OH IOL MAX for the respective pin (A) IOH MIN for the respective pin(A) 1.5 V 150-pF typical load-circuit capacitance(B) Where: IOL = IOH = VLOAD = CL = A. B. For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range" table. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted. Figure 4. Test Load Circuit Submit Documentation Feedback 25 ADVANCE INFORMATION pF TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Timing Parameter Symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: CM CO ER ICLK M OSC, OSCI OSCO P R R0 Compaction, CMPCT CLKOUT Erase Interface clock Master mode OSCIN OSCOUT Program, PROG Ready Read margin 0, RDMRGN0 Read margin 1, RDMRGN1 RD RST RX S SCC SIMO SOMI SPC SYS TX Read Reset, RST SCInRX Slave mode SCInCLK SPInSIMO SPInSOMI SPInCLK System clock SCInTX ADVANCE INFORMATION R1 Lowercase subscripts and their meanings are: a c d f h access time cycle time (period) delay time fall time hold time r su t v w rise time setup time transition time valid time pulse duration (width) The following additional letters are used with these meanings: H L V High Low Valid X Z Unknown, changing, or don't care level High impedance 26 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 External Reference Resonator/Crystal Oscillator Clock Option The oscillator is enabled by connecting the appropriate fundamental 4-20 MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 5b. OSCIN OSCOUT OSCIN OSCOUT C1(A) Crystal C2(A) External Clock Signal (toggling 0-1.8 V) (b) (a) A. The values of C1 and C2 should be provided by the resonator/crystal vendor. Figure 5. Crystal/Clock Connection Submit Documentation Feedback 27 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com ZPLL AND CLOCK SPECIFICATIONS Timing Requirements for ZPLL Circuits Enabled or Disabled MIN f(OSC) tc(OSC) tw(OSCIL) tw(OSCIH) f(OSCRST) (1) Input clock frequency Cycle time, OSCIN Pulse duration, OSCIN low Pulse duration, OSCIN high OSC FAIL frequency (1) 4 50 15 15 53 MAX 20 UNIT MHz ns ns ns kHz Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number SPNU189). Switching Characteristics Over Recommended Operating Conditions for Clocks (1) (2) PARAMETER f(SYS) System clock frequency (4) System clock frequency Interface clock frequency External clock output frequency for ECP module Cycle time, system clock Cycle time, system clock Cycle time, interface clock Cycle time, ECP module external clock output Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Pipeline mode enabled Pipeline mode disabled Flash config mode 16.7 41.6 41.6 40 40 41.6 TEST CONDITIONS (3) Pipeline mode enabled Pipeline mode disabled Flash config mode MIN MAX 60 24 24 25 25 24 UNIT MHz MHz MHz MHz MHz MHz ns ns ns ns ns ns ADVANCE INFORMATION f(CONFIG) f(ICLK) f(ECLK) tc(SYS) tc(CONFIG) tc(ICLK) tc(ECLK) (1) (2) (3) (4) When PLLDIS = 0, f(SYS) = M x f(OSC)/R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8}. R is the system-clock divider determined by the CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit (GLBCTRL.3). When PLLDIS = 1, f(SYS) = f(OSC)/R, where R = {1,2,3,4,5,6,7,8}. f(ICLK) = f(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module. f(ECLK) = f(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module. Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0). Flash Vread must be set to 5 V to achieve maximum system clock frequency. 28 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 Switching Characteristics Over Recommended Operating Conditions for External Clocks (1) (2) (3) (see Figure 6 and Figure 7) PARAMETER tw(COL) Pulse duration, CLKOUT low TEST CONDITIONS SYSCLK or MCLK (4) ICLK: X is even or 1 (5) ICLK: X is odd and not SYSCLK or MCLK (4) tw(COH) Pulse duration, CLKOUT high ICLK: X is even or 1 (5) ICLK: X is odd and not tw(EOL) Pulse duration, ECLK low N is odd and X is even N is odd and X is odd and not 1 N is even and X is even or odd tw(EOH) Pulse duration, ECLK high N is odd and X is even N is odd and X is odd and not 1 (1) (2) (3) (4) (5) 1 (5) N is even and X is even or odd 1 (5) MIN 0.5tc(SYS) - tf 0.5tc(ICLK) - tf 0.5tc(ICLK) + 0.5tc(SYS) - tf 0.5tc(SYS) - tr 0.5tc(ICLK) - tr 0.5tc(ICLK) - 0.5tc(SYS) - tr 0.5tc(ECLK) - tf 0.5tc(ECLK) - tf 0.5tc(ECLK) + 0.5tc(SYS) - tf 0.5tc(ECLK) - tr 0.5tc(ECLK) - tr 0.5tc(ECLK) - 0.5tc(SYS) - tr ns ns ns ns MAX UNIT tw(COH) CLKOUT tw(COL) Figure 6. CLKOUT Timing Diagram tw(EOH) ECLK tw(EOL) Figure 7. ECLK Timing Diagram Submit Documentation Feedback 29 ADVANCE INFORMATION X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module. N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module. CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active. Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary). Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary). TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com RST AND PORRST TIMINGS Timing Requirements for PORRST (see Figure 8) MIN VCCPORL VCCPORH VCCIOPORL VCCIOPORH VIL VIL(PORRST) tsu(PORRST)r tsu(VCCIO)r th(PORRST)r tsu(PORRST)f VCC low supply level when PORRST must be active during power up VCC high supply level when PORRST must remain active during power up and become active during power down VCCIO low supply level when PORRST must be active during power up VCCIO high supply level when PORRST must remain active during power up and become active during power down Low-level input voltage after VCCIO > VCCIOPORH Low-level input voltage of PORRST before VCCIO > VCCIOPORL Setup time, PORRST active before VCCIO > VCCIOPORL during power up Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL Hold time, PORRST active after VCC > VCCPORH Setup time, PORRST active before VCC VCCPORH during power down Hold time, PORRST active after VCC > VCCIOPORH Hold time, PORRST active after VCC < VCCPORL Setup time, PORRST active before VCC VCCIOPORH during power down Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL V CCIOPORH V CCIO MAX UNIT 0.6 V V 1.1 2.75 0.2 VCCIO 0.5 V V V V ms ms ms s ms ms ns ns 1.5 0 0 1 8 1 0 0 0 V CCIOPORH tsu(VCCIO)f ADVANCE INFORMATION th(PORRST)rio th(PORRST)d tsu(PORRST)fio tsu(VCCIO)f V CCP /VCCIO th(PORRST)rio V CC V CCPORH tsu(PORRST)f th(PORRST)r V CC tsu(PORRST)fio tsu(PORRST)f th(PORRST)r V CCPORL th(PORRST)d VIL VIL V IL V IL(PORRST) V CCPORH V CCIOPORL V CC VCCP/VCCIO PORRST V CCPORL tsu(VCCIO)r tsu(PORRST)r V IL(PORRST) V IL V CCIOPORL NOTE: VCCIO > 1.1 V before VCC > 0.6 V Figure 8. PORRST Timing Diagram Switching Characteristics Over Recommended Operating Conditions for RST (1) PARAMETER tv(RST) tfsu Valid time, RST active after PORRST inactive Valid time, RST active (all others) Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump stabilization time) MIN 4112tc(OSC) 8tc(SYS) 716tc(OSC) MAX UNIT ns ns (1) Specified values do NOT include rise/fall times. For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. 30 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 JTAG SCAN INTERFACE TIMING (JTAG Clock Specification 10-MHz and 50-pF Load on TDO Output) MIN tc(JTAG) tsu(TDI/TMS - TCKr) th(TCKr th(TCKf td(TCKf -TDI/TMS) -TDO) -TDO) MAX UNIT ns ns ns ns Cycle time, JTAG low and high period Setup time, TDI, TMS before TCK rise (TCKr) Hold time, TDI, TMS after TCKr Hold time, TDO after TCKf Delay time, TDO valid after TCK fall (TCKf) 50 15 15 10 45 ns TCK tc(JTAG) TMS TDI tc(JTAG) TDO th(TCKf TDO) td(TCKf TDO) Figure 9. JTAG Scan Timings Submit Documentation Feedback 31 ADVANCE INFORMATION tsu(TDI/TMS TCKr) th(TCKr TDI/TMS) TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com OUTPUT TIMINGS Switching Characteristics for Output Timings versus Load Capacitance (CL) (see Figure 10) PARAMETER CL = 15 pF tr Rise time, CLKOUT, AWD, TDO CL = 50 pF CL = 100 pF CL = 150 pF CL = 15 pF tf Fall time, CLKOUT, AWD, TDO CL = 50 pF CL = 100 pF CL = 150 pF CL = 15 pF tr Rise time, SPInCLK, SPInSOMI, SPInSIMO (1) CL = 50 pF CL = 100 pF CL = 150 pF CL = 15 pF tf Fall time, RST, SPInCLK, SPInSOMI, SPInSIMO (1) CL = 50 pF CL = 100 pF CL = 150 pF CL = 15 pF tr Rise time, all other output pins CL = 50 pF CL = 100 pF CL = 150 pF CL = 15 pF tf Fall time, all other output pins CL = 50 pF CL = 100 pF CL = 150 pF (1) Where n = 1-3. tr Output 20% 80% 80% 20% tf VCC MIN 0.5 1.5 3 4.5 0.5 1.5 3 4.5 2.5 5 9 13 2.5 5 9 13 2.5 6.0 12 18 3 8.5 16 23 MAX 2.5 5 9 12.5 2.5 5 9 12.5 8 14 23 32 8 14 23 32 12 28 50 73 12 28 50 73 UNIT ns ns ns ADVANCE INFORMATION ns ns ns 0 Figure 10. CMOS-Level Outputs 32 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 INPUT TIMINGS Timing Requirements for Input Timings (1) (see Figure 11) MIN tpw (1) Input minimum pulse width tc(ICLK) = interface clock cycle time = 1/f(ICLK) tpw Input 20% 80% 80% 20% V CC MAX UNIT ns tc(ICLK) + 10 0 Figure 11. CMOS-Level Inputs FLASH TIMINGS Timing Requirements for Program Flash (1) MIN tprog(16-bit) tprog(Total) terase(sector) twec tfp(RST) tfp(SLEEP) tfp(STDBY) (1) (2) Half word (16-bit) programming time 512K-byte programming time (2) Sector erase time Write/erase cycles at TA = -40C to 125C Flash pump setting time from RST to SLEEP Initial flash pump setting time from SLEEP to STANDBY Initial flash pump setting time from STANDBY to ACTIVE 50000 143tc(SYS) 143tc(SYS) 72tc(SYS) 4 TYP 16 4 1.7 MAX 200 15 UNIT s s s cycles ns ns ns For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet. The 512K-byte programming time includes overhead of state machine. Submit Documentation Feedback 33 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com SPIn MASTER MODE TIMING PARAMETERS SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 12) NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M td(SPCH-SIMO)M td(SPCL-SIMO)M tv(SPCL-SIMO)M tv(SPCH-SIMO)M tsu(SOMI-SPCL)M tsu(SOMI-SPCH)M tv(SPCL-SOMI)M tv(SPCH-SOMI)M Cycle time, SPInCLK (4) Pulse duration, SPInCLK high (clock polarity = 0) Pulse duration, SPInCLK low (clock polarity = 1) Pulse duration, SPInCLK low (clock polarity = 0) Pulse duration, SPInCLK high (clock polarity = 1) Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0) Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1) Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) Setup time, SPInSOMI before SPInCLK low (clock polarity = 0) Setup time, SPInSOMI before SPInCLK high (clock polarity = 1) Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0) Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1) tc(SPC)M - 5 - tf tc(SPC)M - 5 - tr 6 6 4 4 MIN 100 0.5tc(SPC)M - tr 0.5tc(SPC)M - tf 0.5tc(SPC)M - tf 0.5tc(SPC)M - tr MAX 256tc(ICLK) 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 10 10 UNIT ns ns ns ns ns ns ns ADVANCE INFORMATION 7 (5) (1) (2) (3) (4) (5) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. tc(ICLK) = interface clock cycle time = 1/f(ICLK) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. When the SPI is in master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M (PS +1)tc(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. For PS values of 0: tc(SPC)M = 2tc(ICLK) 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSIMO Master Out Data Is Valid 6 7 SPInSOMI Master In Data Must Be Valid Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0) 34 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 SPIn Master Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 13) NO. 1 2 (5) 3 (5) tc(SPC)M tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M tv(SIMO-SPCH)M 4 (5) tv(SIMO-SPCL)M tv(SPCH-SIMO)M 5 (5) tv(SPCL-SIMO)M 6 (6) Cycle time, SPInCLK (4) Pulse duration, SPInCLK high (clock polarity = 0) Pulse duration, SPInCLK low (clock polarity = 1) Pulse duration, SPInCLK low (clock polarity = 0) Pulse duration, SPInCLK high (clock polarity = 1) Valid time, SPInCLK high after SPInSIMO data valid (clock polarity = 0) Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1) Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) Setup time, SPInSOMI before SPInCLK low (clock polarity = 1) Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) MIN 100 0.5tc(SPC)M - tr 0.5tc(SPC)M - tf 0.5tc(SPC)M - tf 0.5tc(SPC)M - tr 0.5tc(SPC)M - 15 ns 0.5tc(SPC)M - 15 0.5tc(SPC)M - 5 - tr ns 0.5tc(SPC)M - 5 - tf 6 6 4 ns 4 ns MAX 256tc(ICLK) 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 0.5tc(SPC)M + 5 UNIT ns ns ns tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0) tsu(SOMI-SPCL)M tv(SPCH-SOMI)M 7 (6) tv(SPCL-SOMI)M (1) (2) (3) (4) (5) (6) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set. tc(ICLK) = interface clock cycle time = 1/f(ICLK) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. When the SPI is in master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M (PS +1)tc(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. For PS values of 0: tc(SPC)M = 2tc(ICLK) 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSIMO Master Out Data Is Valid 6 7 Data Valid SPInSOMI Master In Data Must Be Valid Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1) Submit Documentation Feedback 35 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com SPIn SLAVE MODE TIMING PARAMETERS SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 14) NO. 1 2 (6) 3 (6) tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S td(SPCH4 (6) SOMI)S MIN Cycle time, SPInCLK (5) Pulse duration, SPInCLK high (clock polarity = 0) Pulse duration, SPInCLK low (clock polarity = 1) Pulse duration, SPInCLK low (clock polarity = 0) Pulse duration, SPInCLK high (clock polarity = 1) Delay time, SPInCLK high to SPInSOMI valid (clock polarity = 0) Delay time, SPInCLK low to SPInSOMI valid (clock polarity = 1) Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) Setup time, SPInSIMO before SPInCLK low (clock polarity = 0) Setup time, SPInSIMO before SPInCLK high (clock polarity = 1) Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) tc(SPC)S - 6 - tr 100 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) MAX 256tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 6 + tr UNIT ns ns ns td(SPCLSOMI)S ns 6 + tf tv(SPCH5 (6) SOMI)S tv(SPCLSOMI)S ns tc(SPC)S - 6 - tf 6 ns 6 6 ns 6 ADVANCE INFORMATION tsu(SIMO6(6) SPCL)S tsu(SIMOSPCH)S tv(SPCL7(6) SIMO)S tv(SPCHSIMO)S (1) (2) (3) (4) (5) (6) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared. If the SPI is in slave mode, the following must be true: tc(SPC)S (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5]. For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. tc(ICLK) = interface clock cycle time = 1/f(ICLK) When the SPIn is in slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S (PS +1)tc(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. For PS values of 0: tc(SPC)S = 2tc(ICLK) 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). 1 SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 5 SPInSOMI SPISOMI Data Is Valid 6 7 SPInSIMO SPISIMO Data Must Be Valid Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0) 36 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 15) NO. 1 2 (6) 3 (6) tc(SPC)S tw(SPCH)S tw(SPCL)S tw(SPCL)S tw(SPCH)S tv(SOMI-SPCH)S 4 (6) tv(SOMI-SPCL)S tv(SPCH-SOMI)S 5 (6) tv(SPCL-SOMI)S tsu(SIMO-SPCH)S 6(6) tsu(SIMO-SPCL)S tv(SPCH-SIMO)S 7(6) tv(SPCL-SIMO)S (1) (2) (3) (4) (5) (6) Cycle time, SPInCLK (5) Pulse duration, SPInCLK high (clock polarity = 0) Pulse duration, SPInCLK low (clock polarity = 1) Pulse duration, SPInCLK low (clock polarity = 0) Pulse duration, SPInCLK high (clock polarity = 1) Valid time, SPInCLK high after SPInSOMI data valid (clock polarity = 0) Valid time, SPInCLK low after SPInSOMI data valid (clock polarity = 1) Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) Setup time, SPInSIMO before SPInCLK high (clock polarity = 0) Setup time, SPInSIMO before SPInCLK low (clock polarity = 1) Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) MIN 100 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 0.25tc(ICLK) 0.5tc(SPC)S - 6 - tr ns 0.5tc(SPC)S - 6 - tf 0.5tc(SPC)S - 6 - tr ns 0.5tc(SPC)S - 6 - tf MAX 256tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) 0.5tc(SPC)S + 0.25tc(ICLK) UNI T ns ns ns ns 6 6 ns 6 The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set. If the SPI is in slave mode, the following must be true: tc(SPC)S (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5]. For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. tc(ICLK) = interface clock cycle time = 1/f(ICLK) When the SPIn is in slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S (PS +1)tc(ICLK) 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. For PS values of 0: tc(SPC)S = 2tc(ICLK) 100 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1). Submit Documentation Feedback 37 ADVANCE INFORMATION 6 TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 1 www.ti.com SPInCLK (clock polarity = 0) 2 3 SPInCLK (clock polarity = 1) 4 5 SPInSOMI SPISOMI Data Is Valid 6 7 Data Valid ADVANCE INFORMATION 38 SPInSIMO SPISIMO Data Must Be Valid Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1) Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK Timing Requirements for Internal Clock SCIn Isosynchronous Mode (1) (2) (3) (see Figure 16) (BAUD + 1) IS EVEN OR BAUD = 0 MIN tc(SCC) tw(SCCL) tw(SCCH) td(SCCH-TXV) Cycle time, SCInCLK Pulse duration, SCInCLK low Pulse duration, SCInCLK high Delay time, SCInCLK high to SCInTX valid Valid time, SCInTX data after SCInCLK low Setup time, SCInRX before SCInCLK low Valid time, SCInRX data after SCInCLK low tc(SCC) - 10 2tc(ICLK) 0.5tc(SCC) - tf 0.5tc(SCC) - tr MAX 224 tc(ICLK) 0.5tc(SCC) + 5 0.5tc(SCC) + 5 10 MIN 3tc(ICLK) 0.5tc(SCC) + 0.5tc(ICLK) - tf 0.5tc(SCC) - 0.5tc(ICLK) - tr (BAUD + 1) IS ODD AND BAUD 0 MAX (224 - 1) tc(ICLK) 0.5tc(SCC) + 0.5tc(ICLK) 0.5tc(SCC) - 0.5tc(ICLK) 10 UNI T ns ns ns ns tv(TX) tc(SCC) - 10 ns tsu(RX-SCCL) tc(ICLK) + tf + 20 tc(ICLK) + tf + 20 ns tv(SCCL-RX) -tc(ICLK) + tf + 20 -tc(ICLK) + tf + 20 ns (1) (2) (3) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers. tc(ICLK) = interface clock cycle time = 1/f(ICLK) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. tc(SCC) tw(SCCL) SCICLK td(SCCH TXV) SCITX tsu(RX SCCL) tv(TX) tw(SCCH) Data Valid tv(SCCL RX) SCIRX Data Valid A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock Submit Documentation Feedback 39 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK Timing Requirements for External Clock SCIn Isosynchronous Mode (1) (2) (see Figure 17) MIN tc(SCC) tw(SCCH) tw(SCCL) td(SCCH-TXV) tv(TX) tsu(RX-SCCL) tv(SCCL-RX) (1) (2) (3) Cycle time, SCInCLK (3) Pulse duration, SCInCLK high Pulse duration, SCInCLK low Delay time, SCInCLK high to SCInTX valid Valid time, SCInTX data after SCInCLK low Setup time, SCInRX before SCInCLK low Valid time, SCInRX data after SCInCLK low 2tc(SCC) - 10 0 2tc(ICLK) + 10 8tc(ICLK) 0.5tc(SCC) - 0.25tc(ICLK) 0.5tc(SCC) - 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) 0.5tc(SCC) + 0.25tc(ICLK) 2tc(ICLK) + 12 + tr MAX UNIT ns ns ns ns ns ns ns tc(ICLK) = interface clock cycle time = 1/f(ICLK) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table. When driving an external SCInCLK, the following must be true: tc(SCC) 8tc(ICLK). tc(SCC) ADVANCE INFORMATION 40 tw(SCCH) tw(SCCL) SCICLK tv(TX) td(SCCH TXV) SCITX tsu(RX SCCL) Data Valid Data Valid tv(SCCL RX) SCIRX A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK falling edge. Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 HIGH-END TIMER (HET) TIMINGS Minimum PWM Output Pulse Width: This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes. Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns Minimum Input Pulses that Can Be Captured: The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32. Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is, the captured value gives the number of HRP clocks inside the pulse.) Abbreviations: hr = HET high resolution divide rate = 1, 2, 3,...63, 64 lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32 High resolution clock period = HRP = hr/SYSCLK Loop resolution clock period = LRP = hr*lr/SYSCLK HIGH-END CAN CONTROLLER (HECCn) MODE TIMINGS Dynamic Characteristics for the CANnHTX and CANnHRX Pins PARAMETER td(CANnHTX) td(CANnHRX) (1) Delay time, transmit shift register to CANnHTX pin (1) Delay time, CANnHRX pin to receive shift register MIN MAX 15 5 UNIT ns ns These values do not include rise/fall times of the output buffer. Submit Documentation Feedback 41 ADVANCE INFORMATION NOTE: TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com MULTI-BUFFERED A-TO-D CONVERTER (MibADC) The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on VSS and VCC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Resolution Monotonic Output conversion code 10 bits (1024 values) Assured 00h to 3FFh [00 for VAI ADREFLO; 3FF for VAI ADREFHI] Table 10. MibADC Recommended Operating Conditions (1) MIN ADREFHI ADREFLO VAI IAIC (1) (2) A-to-D high-voltage reference source A-to-D low-voltage reference source Analog input voltage Analog input clamp (VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3) current (2) VSSAD VSSAD VSSAD - 0.3 -2 MAX VCCAD VCCAD VCCAD + 0.3 2 UNIT V V V mA ADVANCE INFORMATION For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table. Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. Table 11. Operating Characteristics Over Full Ranges of Recommended Operating Conditions (1) (2) PARAMETER RI CI IAIL IADREFHI CR EDNL Analog input resistance Analog input capacitance Analog input leakage current ADREFHI input current Conversion range over which specified accuracy is maintained Differential nonlinearity error DESCRIPTION/CONDITIONS See Figure 18. See Figure 18. See Figure 18. ADREFHI = 3.6 V, ADREFLO = VSSAD ADREFHI - ADREFLO Difference between the actual step width and the ideal value. See Figure 19. Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. See Figure 20. Maximum value of the difference between an analog value and the ideal midstep value. See Figure 21. 3 Conversion Sampling -1 MIN TYP 250 MAX UNIT 500 10 30 1 5 3.6 pF pF A mA V 1.5 LSB EINL Integral nonlinearity error 2 LSB E TOT (1) (2) Total error/absolute accuracy 2 LSB VCCAD = ADREFHI 1 LSB = (ADREFHI - ADREFLO)/ 210 for the MibADC 42 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 External Rs MibADC Input Pin Ri Sample Switch V src Parasitic Capacitance Sample Capacitor R leak Ci Figure 18. MibADC Input Equivalent Circuit Multi-Buffer ADC Timing Requirements tc(ADCLK) td(SH) td(c)) td(SHC) (1) (1) Cycle time, MibADC clock Delay time, sample and hold time Delay time, conversion time Delay time, total sample/hold and conversion time 0.05 1 0.55 1.55 s s s s This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206). The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 0 ... 101 0 ... 100 0 ... 011 1 LSB 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Analog Input Value (LSB) Differential Linearity Error(1/2 LSB) 1 LSB Differential Linearity Error(- 1/2 LSB) A. 1 LSB = (ADREFHI - ADREFLO)/210 Figure 19. Differential Nonlinearity (DNL) Submit Documentation Feedback 43 ADVANCE INFORMATION MIN NOM MAX UNIT TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) At Transition 011/100 ( 1/2 LSB) End-Point Lin. Error At Transition 001/010 ( 1/4 LSB) Ideal Transition Actual Transition ADVANCE INFORMATION A. 1 LSB = (ADREFHI - ADREFLO)/210 Figure 20. Integral Nonlinearity (INL) Error The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Analog Input Value (LSB) 6 7 Total Error At Step 0 ... 001 (1/2 LSB) Total Error At Step 0 ... 101 (-1 1/4 LSB) A. 1 LSB = (ADREFHI - ADREFLO)/210 Figure 21. Absolute Accuracy (Total) Error 44 Submit Documentation Feedback www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 THERMAL RESISTANCE CHARACTERISTICS PARAMETER RJA RJC C/W 43 6.5 Submit Documentation Feedback 45 ADVANCE INFORMATION TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A - SEPTEMBER 2005 - REVISED AUGUST 2006 www.ti.com Revision History This revision history highlights the changes made to the device-specific datasheet SPNS107. Table 12. Revision History SPNS107 to SPNS107A Revised the Family Nomenclature drawing to add Q version of the temperature range. Revised "Absolute Maximum Ratings" table to add Q version of the temperature range. Revised "Device Recommended Operating Conditions" table to add Q version of the temperature range. Added note to PORRST Timing Diagram. Changed TA range to -40C to 125C on twec in "Timing Requirements for Program Flash" table. Added twec MIN value of 50000 and deleted MAX value in "Timing Requirements for Program Flash" table. Changed terase(sector) TYP value to 1.7 and removed MAX value in "Timing Requirements for Program Flash" table. ADVANCE INFORMATION 46 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2006 PACKAGING INFORMATION Orderable Device TMP470R1B512PGE TMS470R1B512PGET (1) Status (1) PREVIEW ACTIVE Package Type LQFP LQFP Package Drawing PGE PGE Pins Package Eco Plan (2) Qty 144 144 1 60 TBD Green (RoHS & no Sb/Br) Lead/Ball Finish Call TI CU NIPDAU MSL Peak Temp (3) Call TI Level-3-260C-168HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF017A - OCTOBER 1994 - REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 37 0,13 NOM 1 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 36 Gage Plane 0,05 MIN 0,25 0- 7 1,45 1,35 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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